The present invention relates generally to semiconductor wafer polishing, and more particularly, to a polishing inhibiting layer forming additive for a slurry, the slurry so formed, and a method of chemical mechanical polishing.
In the semiconductor industry, chemical mechanical polishing (CMP) is used to smooth, planarize, and/or remove layers during the fabrication process. During CMP, a slurry is dispersed over the surface to be polished as a polishing pad rotates in contact with the surface to smooth, planarize and/or remove the surface. One problem with conventional CMP processes and slurries is that they do not perfectly planarize a surface, especially those that have a variety of pattern densities or have an uneven topography. For example, FIG. 1 shows an illustrative surface topography of a semiconductor wafer 8 including a raised location A that is higher than a recessed location B. Typically, a polishing rate of a surface is considered equivalent to a slurry's coefficient of friction (k) times polishing pressure (sometimes referred to as downforce) (P), i.e., polishing rate (PR)=k*P. That is, polishing rate is linear with polishing pressure P. The local polishing pressure, however, is proportional to the localized planarity and pattern density of the location. In the FIG. 1 topography, polishing pressure for location A is greater than the polishing pressure for location B, and planarity is ideally achieved by the rate differential for the locations A, B. In this case, recessed location B is preferably not polished until raised location A is planar therewith. In the topography illustrated in FIG. 1, however, a number of factors result in a non-zero polishing rate in recessed location B even though polishing pad 10 never contacts the surface. One factor that causes this problem is slurry above recessed location B still provides a modicum of polishing, which may destroy recessed location B. Another factor is the flexibility of a polishing pad 10, which causes recessed location B to be polished even though not desired.
Another factor is the geometric lengthscales of the features to be polished as compared to the “planarization length” (Lp) of the process. “Planarization length” can be thought of as the lengthscale of the pad that can bend and conform. If a pad is very rigid, it is flat and will tend to flatten things over a very long distance relative to a chip wire dimension (microns). If the polishing pad is very flexible this length is much shorter and the pad can bend and conform to items that are closer together. Accordingly, if, for example, two large, dense supporting features (e.g., points A in FIG. 1) are provided on a wafer at a distance (L) apart and one or more less dense random structures (e.g., structure B in FIG. 1) fill the space(s) between them, it is advantageous to know at what lengthscale L those inner structures will be protected by the large structures. That length of protection varies with the pad to the first order (slurry and other things to 2nd order) and is called the “planarization length.” When Lp>L, those features would be protected from detrimental polishing.
Referring to FIGS. 2A-2H, the above-described problems are further illustrated relative to a wafer 18 (FIG. 2A only) including a location A having a somewhat less dense pattern formation than a location B. As illustrated, through time=0-2 (FIGS. 2A-2C), polishing progresses non-uniformly due to the pattern density differences between location A and location B. In particular, as shown in FIG. 2G, due to the different densities, localized pressure at location A (PA) and B (PB) are different, which results in different polishing rates (PR), i.e., PA>PB, PRA>PRB. As polishing progresses through time=2, 3 and 4 (FIGS. 2C-2E), the disparity between polishing rates of location A and B, results in a much faster removal of material for location A. As shown in FIG. 2D, eventually, the low-density location A is planarized such that location A becomes 100% filled. At this point, the polishing pressure becomes uniform and equal to the total applied pressure. However, the pressure at higher points, e.g., location B, remains high. As shown in FIG. 2H, this results in PA<PB, PRA<PRB. Note, however, that PRA is non-zero. The result of this polishing is shown in FIG. 2E, in which location A is rutted and nonplanar with location B. In contrast, FIG. 2F illustrates the intended result in which location A and B are planar, i.e., PA=PB, and PRA=PRB. This structure is obtained through conventional polishing only after long time periods of polishing, where the planarity is achieved at the expense of thinning the thickness of the total film stack.
Surfactants have been added to slurries to improve removal selectivity. For example, U.S. Pat. No. 6,514,862 to Lee et al., discloses a wafer polishing slurry and CMP method in which a surfactant is added. In this case, however, the surfactant is meant to form a non-removable layer, which does not address the above-described problems.
In view of the foregoing, there is a need in the art for a way to address the problems of the related art.